
2006 Microchip Technology Inc.
DS41159E-page 29
PIC18FXX8
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD)
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
1V
5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
IINTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note:
TOST = 1024 clock cycles.
TPLL
≈ 2 ms max. First three stages of the PWRT timer.